Fabricating semiconductor devices such as logic and memory devices typically includes processing a substrate such as a semiconductor wafer using a large number of semiconductor fabrication processes to form various features and multiple levels of the semiconductor devices. For example, lithography is a semiconductor fabrication process that involves transferring a pattern from a reticle to a resist arranged on a semiconductor wafer. Additional examples of semiconductor fabrication processes include, but are not limited to, chemical-mechanical polishing (CMP), etching, deposition, and ion implantation. Multiple semiconductor devices may be fabricated in an arrangement on a single semiconductor wafer and then separated into individual semiconductor devices.
As used throughout the present disclosure, the term “wafer” generally refers to substrates formed of a semiconductor or non-semiconductor material. For example, a semiconductor or non-semiconductor material may include, but are not limited to, monocrystalline silicon, gallium arsenide, and indium phosphide. A wafer may include one or more layers. For example, such layers may include, but are not limited to, a resist, a dielectric material, a conductive material, and a semiconductive material. Many different types of such layers are known in the art, and the term wafer as used herein is intended to encompass a wafer on which all types of such layers may be formed. One or more layers formed on a wafer may be patterned or unpatterned. For example, a wafer may include a plurality of dies, each having repeatable patterned features. Formation and processing of such layers of material may ultimately result in completed devices. Many different types of devices may be formed on a wafer, and the term wafer as used herein is intended to encompass a wafer on which any type of device known in the art is being fabricated.
Metrology processes are used at various steps during a semiconductor manufacturing process to monitor process control during device fabrication. One such metrology process includes critical dimension (CD) metrology. CD metrology may be implemented utilizing a focus and exposure matrix (FEM) wafer.
Such approaches may include the use of test target structures having nominal parameters, such line width, sidewall angle and height. Scatterometry/ellipsometry based spectra may be collected from test targets for all combinations (if possible) of focus and exposure in a focus-expose matrix on a test wafer and stored in a library. Then, during measurement a closest match is found in the stored library for each spectrum and the corresponding structure parameters (e.g., line width, sidewall angle, line height, etc.) for the library matches are matched with the programmed focus and exposure combinations from the FEM test wafer.
As the dimensions of semiconductor devices decrease, CD metrology processes become even more important to the successful manufacture of acceptable semiconductor devices. As such, it would be advantageous to provide a system and method that provides improved CD metrology capabilities.